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Yazar "Kaymak, Nuriye" seçeneğine göre listele

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    3D-graphene-laser patterned p-type silicon Schottky diode
    (Elsevier Sci Ltd, 2021) Orhan, Elif Oz; Efil, Esra; Bayram, Ozkan; Kaymak, Nuriye; Berberoglu, Halil; Candemir, Ozun; Pavlov, Ihor
    The influence of the laser patterning (LP) process on the quality of graphene (Gr) film and Schottky diode characteristics was researched in this study. First of all, p-type silicon (Si) was patterned by homemade femto-second laser source. To compare the resulting effect, non-patterned n-Si and p-Si were used as substrates. To achieve vertically oriented three-dimensional (3D) Gr nanosheets (VGNs) onto the laser patterned p-type Si, non patterned n-Si, and p-Si substrates, we used Radio-Frequency Plasma Enhanced Chemical Vapor Deposition (RFPECVD) technique. Then, Raman analyses for VGNs obtained on patterned and non-patterned p-Si and n-Si substrates were conducted. All results indicate that the Gr obtained on all substrates is vertically oriented. Scanning electron microscopy (SEM) analyses were also performed to obtain information about the morphological properties of the 3D Gr structure. In addition, the influence of the laser patterning at the Gr-Si interface was evaluated by comparing two sets of devices which are junctions of Gr-Laser Patterned Si (Gr-LPSi) and GrInsulator-Silicon (Gr-I-Si) at 300 K in the dark medium. D1 device consists of a Gr-LPSi junction that involves RFPECVD grown Gr on the silicon, whose surface exposed the laser beam for patterning. D2 device consists of a GrI-Si junction that involves RF-PECVD grown Gr onto the silicon, whose surface involves a thin native oxide layer (similar to 2 nm). The results show that the laser treatment causes an increment in Schottky barrier height (SBH) and decreases leakage currents under a reverse bias voltage of the diode. Notably, we have seen the influence of the laser patterning process on 3D Gr nano-sheets which is that the entire surface of the substrate has now reformed new structures in the nano-sphere and nano-rose morphology, so we believe that this is the first work that shows these structures in this form.
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    Current voltage analyses of Graphene-based structure onto Al2O3/p-Si using various methods
    (Pergamon-Elsevier Science Ltd, 2020) Efil, Esra; Kaymak, Nuriye; Seven, Elanur; Orhan, Elif Oz; Bayram, Ozkan; Ocak, Sema Bilge; Tataroglu, Adem
    The present study's main purpose is to determine the current-voltage (I-V) performance of Graphene (Gr) based hetero nanostructure produced on Al2O3/p-Si. Graphene synthesis was carried out using the chemical vapor deposition (CVD) technique on Copper (Cu) foils used as a metal catalyst and transferred onto Al2O3/p-Si using the conventional transfer method. The I-V characteristics of this structure were measured in the dark environment, and the electrical properties of the Gr/Si structure were characterized at room temperature. The rectifying ratio (RR) of the structure was found to be about 103 at +/- 3 V. The electrical properties of ideality factor (n), series resistance (R-S), and barrier height (Phi(b)) were examined by using the theory of Thermionic Emission (TE), Norde's method, and Cheung's method. The values of Phi(b), which were calculated using Norde's method, Cheung's method, and the theory of thermionic emission (TE), were found to be 0.69 eV, 0.71 eV, and 0.68 eV, respectively. The ideality factor was found to be approximately 3.89 according to the theory of TE. The values of series resistance were also determined using the Norde's method and Cheung's two different parameters (dV/dln (I) and H(I)) found to be 9.60 k Omega, 9.12 k Omega, and 5.94 k Omega, respectively.
  • Küçük Resim Yok
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    Dielectric characteristics and electrical conductivity behavior of graphene/Al2O3/p-type silicon structure
    (Elsevier Science Sa, 2021) Kaymak, Nuriye; Orhan, Elif Oz; Bayram, Ozkan; Ocak, Sema Bilge
    Graphene nanosheets (Gns) obtained by the chemical vapor deposition (CVD) method have been employed for the fabrication of Graphene/Al2O3/p-type silicon (Si) structure. The Raman, scanning-electron-microscopy (SEM) and transmission-electron-microscopy (TEM) have been used to analyze the morphology and structural features of the graphene nanosheet. The dielectric features and electrical-conductivity of Graphene/Al2O3/p-type Si have been studied in the frequency range 10 kHz-400 kHz and in the voltage range,-4 V to +4 V at 300 K. The obtained experimental outcomes imply that electrical conductivity and dielectric features of Graphene/ Al2O3/p-type Si were found out to be powerful functions of frequency and applied bias voltage. It can be seen that almost all of the interface states between metal and silicon contribute to modify of dielectric features of Graphene/Al2O3/p-type Si structure.
  • Küçük Resim Yok
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    Electrical properties of Graphene/Silicon structure with Al2O3 interlayer
    (Springer, 2020) Kaymak, Nuriye; Bayram, Ozkan; Tataroglu, Adem; Ocak, Sema Bilge; Orhan, Elif Oz
    The electrical properties of the fabricated Al/Gr/Al2O3/p-Si structure have been analyzed using frequency-dependent capacitance/conductance-voltage (C/G-V) measurements. Graphene (Gr) nanosheets were grown on to copper (Cu) catalyst substrate, which has 99.99% purity, by Chemical Vapor Deposition (CVD) technique, and then the Graphene was transferred on -Al2O3/p-Si by the standard transfer process. The Graphene structures have been characterized by Raman Spectroscopy and Transmission Electron Microscopy (TEM) analyses, and the results of both analyses confirmed the monolayer/bilayer Graphene nanostructure. The forward and reverse bias G- V and C-V measurements of this structure have been performed in 10 kHz-400 kHz and at 300 K. The frequency dispersion in C and G can be evaluated for interface state density ( D it) and series resistance ( R s) values. The values of D it and R s are dependent on frequency and increase with decreasing frequency. The R s - V graph shows a peak form at all frequencies in the depletion region and vanishes with increasing frequency. The obtained results suggest that the prepared structure can be used in electronic device applications.

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