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    Analysing the potential of transport triggered architecture for lattice-based cryptography algorithms
    (Inderscience Enterprises Ltd, 2022) Akcay, Latif; Yalcin, Berna Ors
    Lattice-based structures offer numerous possibilities for post-quantum cryptography. Recently, many post-quantum cryptography algorithms have been built on hard lattice problems. The three of the remaining four algorithms in the final round of the NIST Standardization Process rely on lattice-based methods. However, suitable processor architectures for these algorithms have not been sufficiently investigated. This study examines the potential advantages of transport triggered architecture for these algorithms. We compare popular 64-bit RISC-V processors with our conceptual transport triggered architecture processor over reference software implementations. Our processor provides better results than RISC-V competitors, regardless of the algorithm. It seems to be up to 3x faster, 1.6x-2x smaller, and consumes 1.3x-3.6x less energy than the compared RISC-V cores. Thus, an alternative base architecture is proposed for post-quantum cryptography processor development for embedded systems. The most critical shortcoming of the proposed architecture is the lack of compatible intellectual property core support for system-on-chip designs. We share comparative analyses with test results for different core configurations.
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    Implementation of a SoC by Using lowRISC Architecture on an FPGA for Image Filtering Applications
    (Institute of Electrical and Electronics Engineers Inc., 2022) Akcay, Latif; Surer, Bartu; Yalcin, Berna Ors
    In this study, it is aimed to implement the low-RISC system-on-chip, which is based on the Rocket processor created with the RISC-V instruction set architecture developed by Berkeley University, on FPGA and to run image processing algorithms on this system. While making this implementation, the main target is a system that is very simple, consumes low power, and can be quickly redirected to other purposes. Therefore, it is based on the effective evaluation of the existing system without using any extra customized accelerators. Thus, a free, open source, and powerful enough platform for many embedded system applications is proposed to the designers. For this purpose, a lane detection application designed with standard C libraries such as Gaussian blur filter, Sobel operation filter and other elements, which are widely used in image processing applications, is run with embedded Linux operating system and the results are shared. © 2022 IEEE.
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    Lightweight ASIP Design for Lattice-Based Post-quantum Cryptography Algorithms
    (Springer Heidelberg, 2024) Akcay, Latif; Yalcin, Berna Ors
    Lattice-based cryptography (LBC) algorithms are considered suitable candidates for post-quantum cryptography (PQC), as they dominate the standardization process put forward by the National Institute of Standards and Technology (NIST). Indeed, three of the four key encapsulation mechanism (KEM) algorithms in the third round of the process are based on computationally hard lattice problems. On the other hand, there is an urgent need for processor designs that can run PQC algorithms efficiently, especially for embedded systems. This study presents an application-specific instruction set processor (ASIP) design for the Kyber, Saber, and NewHope algorithms based on transport triggered architecture (TTA). Custom hardware accelerators are added to the baseline processor architecture for computation-intensive steps without applying any software optimization to the reference code. We compared FPGA and ASIC implementations of our design with the prominent RISC-V cores and instruction set extension studies in the literature. According to the results, the proposed design offers greater efficiency, better performance, and lower resource utilization than its competitors in most cases.