Lightweight ASIP Design for Lattice-Based Post-quantum Cryptography Algorithms
Küçük Resim Yok
Tarih
2024
Yazarlar
Dergi Başlığı
Dergi ISSN
Cilt Başlığı
Yayıncı
Springer Heidelberg
Erişim Hakkı
info:eu-repo/semantics/openAccess
Özet
Lattice-based cryptography (LBC) algorithms are considered suitable candidates for post-quantum cryptography (PQC), as they dominate the standardization process put forward by the National Institute of Standards and Technology (NIST). Indeed, three of the four key encapsulation mechanism (KEM) algorithms in the third round of the process are based on computationally hard lattice problems. On the other hand, there is an urgent need for processor designs that can run PQC algorithms efficiently, especially for embedded systems. This study presents an application-specific instruction set processor (ASIP) design for the Kyber, Saber, and NewHope algorithms based on transport triggered architecture (TTA). Custom hardware accelerators are added to the baseline processor architecture for computation-intensive steps without applying any software optimization to the reference code. We compared FPGA and ASIC implementations of our design with the prominent RISC-V cores and instruction set extension studies in the literature. According to the results, the proposed design offers greater efficiency, better performance, and lower resource utilization than its competitors in most cases.
Açıklama
Anahtar Kelimeler
Kyber, Saber, NewHope, Transport-triggered architecture, RISC-V, Efficient processor design
Kaynak
Arabian Journal For Science and Engineering
WoS Q Değeri
N/A
Scopus Q Değeri
Q1
