Lightweight ASIP Design for Lattice-Based Post-quantum Cryptography Algorithms

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dc.authoridAkcay, Latif/0000-0003-2580-2643
dc.contributor.authorAkcay, Latif
dc.contributor.authorYalcin, Berna Ors
dc.date.accessioned2024-10-04T18:51:21Z
dc.date.available2024-10-04T18:51:21Z
dc.date.issued2024
dc.departmentBayburt Üniversitesien_US
dc.description.abstractLattice-based cryptography (LBC) algorithms are considered suitable candidates for post-quantum cryptography (PQC), as they dominate the standardization process put forward by the National Institute of Standards and Technology (NIST). Indeed, three of the four key encapsulation mechanism (KEM) algorithms in the third round of the process are based on computationally hard lattice problems. On the other hand, there is an urgent need for processor designs that can run PQC algorithms efficiently, especially for embedded systems. This study presents an application-specific instruction set processor (ASIP) design for the Kyber, Saber, and NewHope algorithms based on transport triggered architecture (TTA). Custom hardware accelerators are added to the baseline processor architecture for computation-intensive steps without applying any software optimization to the reference code. We compared FPGA and ASIC implementations of our design with the prominent RISC-V cores and instruction set extension studies in the literature. According to the results, the proposed design offers greater efficiency, better performance, and lower resource utilization than its competitors in most cases.en_US
dc.description.sponsorshipBayburt Universityen_US
dc.description.sponsorshipWe thank the TCE team for supporting this work and their efforts to improve the toolset.en_US
dc.identifier.doi10.1007/s13369-024-08976-w
dc.identifier.issn2193-567X
dc.identifier.issn2191-4281
dc.identifier.scopus2-s2.0-85191082634en_US
dc.identifier.scopusqualityQ1en_US
dc.identifier.urihttps://doi.org/10.1007/s13369-024-08976-w
dc.identifier.urihttp://hdl.handle.net/20.500.12403/3469
dc.identifier.wosWOS:001205929200004en_US
dc.identifier.wosqualityN/Aen_US
dc.indekslendigikaynakWeb of Scienceen_US
dc.indekslendigikaynakScopusen_US
dc.language.isoenen_US
dc.publisherSpringer Heidelbergen_US
dc.relation.ispartofArabian Journal For Science and Engineeringen_US
dc.relation.publicationcategoryMakale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanıen_US
dc.rightsinfo:eu-repo/semantics/openAccessen_US
dc.subjectKyberen_US
dc.subjectSaberen_US
dc.subjectNewHopeen_US
dc.subjectTransport-triggered architectureen_US
dc.subjectRISC-Ven_US
dc.subjectEfficient processor designen_US
dc.titleLightweight ASIP Design for Lattice-Based Post-quantum Cryptography Algorithmsen_US
dc.typeArticleen_US

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