Speeding up the Discrete Cosine Transform Through Custom Operations and Fixed-Point Arithmetic

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dc.contributor.authorAkçay, Latif
dc.contributor.authorEngın, Mustafa Alptekın
dc.date.accessioned2026-02-28T11:58:21Z
dc.date.available2026-02-28T11:58:21Z
dc.date.issued2025
dc.departmentBayburt Üniversitesi
dc.description.abstractDigital signal processing applications are becoming increasingly important because modern systems work with much larger amounts of data than before. The Discrete Cosine Transform (DCT), used in almost all multimedia compression methods, creates a significant computational load especially in resource-constrained embedded systems. This study proposes four custom operations compatible with Transport-Triggered Architecture (TTA). To enhance computational efficiency and avoid floating-point overhead, fixed-point arithmetic is used. To analyse the effect of the proposed operations, different Application-Specific Instruction Set Processor (ASIP) configurations were created on a general-purpose processor architecture. Performance analyses show that speedups between 2x and 3.5x are achieved. In addition, the developed processor models have been implemented in hardware. FPGA synthesis results indicate a reasonable increase in chip area, showing that the proposed solutions could be an efficient alternative, particularly for limited-resource embedded systems.
dc.identifier.doi10.38088/jise.1712080
dc.identifier.endpage278
dc.identifier.issn2602-4217
dc.identifier.issue2
dc.identifier.startpage268
dc.identifier.trdizinid1370657
dc.identifier.urihttps://doi.org/10.38088/jise.1712080
dc.identifier.urihttps://search.trdizin.gov.tr/tr/yayin/detay/1370657
dc.identifier.urihttps://hdl.handle.net/20.500.12403/5501
dc.identifier.volume9
dc.indekslendigikaynakTR-Dizin
dc.language.isoen
dc.relation.ispartofJournal of Innovative Science and Engineering (JISE)
dc.relation.publicationcategoryMakale - Ulusal Hakemli Dergi - Kurum Öğretim Elemanı
dc.rightsinfo:eu-repo/semantics/openAccess
dc.snmzKA_TR-Dizin_20260218
dc.subjectDiscrete Cosine Transform
dc.subjectSignal processing
dc.subjectEfficient processor design
dc.subjectTransport-Triggered Architecture
dc.subjectApplication-specific processor design
dc.titleSpeeding up the Discrete Cosine Transform Through Custom Operations and Fixed-Point Arithmetic
dc.typeArticle

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