Analysing the potential of transport triggered architecture for lattice-based cryptography algorithms

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dc.authoridOrs, Berna/0000-0003-0851-8501
dc.contributor.authorAkcay, Latif
dc.contributor.authorYalcin, Berna Ors
dc.date.accessioned2024-10-04T18:48:13Z
dc.date.available2024-10-04T18:48:13Z
dc.date.issued2022
dc.departmentBayburt Üniversitesien_US
dc.description.abstractLattice-based structures offer numerous possibilities for post-quantum cryptography. Recently, many post-quantum cryptography algorithms have been built on hard lattice problems. The three of the remaining four algorithms in the final round of the NIST Standardization Process rely on lattice-based methods. However, suitable processor architectures for these algorithms have not been sufficiently investigated. This study examines the potential advantages of transport triggered architecture for these algorithms. We compare popular 64-bit RISC-V processors with our conceptual transport triggered architecture processor over reference software implementations. Our processor provides better results than RISC-V competitors, regardless of the algorithm. It seems to be up to 3x faster, 1.6x-2x smaller, and consumes 1.3x-3.6x less energy than the compared RISC-V cores. Thus, an alternative base architecture is proposed for post-quantum cryptography processor development for embedded systems. The most critical shortcoming of the proposed architecture is the lack of compatible intellectual property core support for system-on-chip designs. We share comparative analyses with test results for different core configurations.en_US
dc.identifier.doi10.1504/IJES.2022.127164
dc.identifier.endpage420en_US
dc.identifier.issn1741-1068
dc.identifier.issn1741-1076
dc.identifier.issue5en_US
dc.identifier.scopus2-s2.0-85144377919en_US
dc.identifier.scopusqualityQ4en_US
dc.identifier.startpage404en_US
dc.identifier.urihttps://doi.org/10.1504/IJES.2022.127164
dc.identifier.urihttp://hdl.handle.net/20.500.12403/2976
dc.identifier.volume15en_US
dc.identifier.wosWOS:000890870400004en_US
dc.identifier.wosqualityN/Aen_US
dc.indekslendigikaynakWeb of Scienceen_US
dc.indekslendigikaynakScopusen_US
dc.language.isoenen_US
dc.publisherInderscience Enterprises Ltden_US
dc.relation.ispartofInternational Journal of Embedded Systemsen_US
dc.relation.publicationcategoryMakale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanıen_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subjecttransport triggered architectureen_US
dc.subjectTTAen_US
dc.subjectRISC-Ven_US
dc.subjectlattice-based cryptographyen_US
dc.subjectpost-quantum cryptographyen_US
dc.subjectPQCen_US
dc.subjectembedded systemsen_US
dc.subjectapplication-specific processoren_US
dc.titleAnalysing the potential of transport triggered architecture for lattice-based cryptography algorithmsen_US
dc.typeArticleen_US

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